PS13201
500MHz 75dB Logarithmic/Limiting Amplifier
Data Sheet 210892 issue 3
Jul-12
FEATURES
•
•
•
•
•
•
•
•
75dB Dynamic Range
Surface Mount SO Package
Adjustable Log Slope and Offset
0dBm RF Limiting Output
60dBm Limiting Range
2V Video Output Range
Low Power (Typ. 1W)
Temperature Range (T
CASE
) -55°C to +125°C
Ordering Information
PS13201 M1C8A4 (
Miniature Ceramic package in tubes)
PS13201 C1C8A4 (
Miniature Ceramic package in tubes)
PS13201 (Probe-tested bare die)
Equivalent Parts
: SL3522
DESCRIPTION
The PS13201 is a monolithic seven stage
successive detection logarithmic amplifier
integrated circuit for use in the 100MHz to
500MHz frequency range.
It features an on-chip video amplifier with
provision for external adjustment of log
slope and offset. It also features a
balanced RF output. The PS13201
operates from supplies of ±5V.
APPLICATIONS
•
•
•
Ultra Wideband Log Receivers
Channelised and Monopulse
Radar
Instrumentation
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Storage Temperature
Junction Temperature
Thermal Resistance
Die-to-case
Die-to-ambient
Applied DC voltage to RF input
Applied RF power to RF input
±6.0V
-65° to +175°
C
C
+175°
C
15.5°
C/W
76.5°
C/W
±400mV
+15dBm
ESD PROTECTION
To
achieve
the
high
frequency
performance there are no ESD protection
structures on the RF input pins (27, 28).
These pins are
highly static sensitive,
typically measured as 250V using MIL-
STD-883 method 3015. Therefore, ESD
handling precautions are
essential
to avoid degradation of performance
or permanent damage to this device.
Fig. 1
Pin connections
top view
Data Sheet 210892 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web:
www.plesseysemi.com
1
PS13201
ELECTRICAL CHARACTERISTICS
The electrical characteristics are guaranteed over the following range of operating conditions, using test circuit in
Fig. 3 (unless otherwise stated):
Temperature range:
Military:
Commercial:
Supply voltage:
V
CC
:
V
EE
:
Frequency
Rg, Ro, Rt
Video output load
PS13201M1C8A4, PS13201
PS13201C1C8A4
+4.50V to +5.50V (all grades)
-4.5V to -5.50V (all grades)
100MHz to 500MHz
1.5K
200 //20pF
-55°C to +125°C (T
CASE
)
0°C to +70°C (T
CASE
)
Test conditions (unless otherwise stated):
Temperature:
PS13201M1C8A4 :+25°C, +125°C & -55°C (T
CASE
)
PS13201C1C8A4 :+25°C
PS13201 : +25°C
Supply voltage:
V
CC
= +5.0V
V
EE
= -5.0V
Data Sheet 210892 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web:
www.plesseysemi.com
2
PS13201
Parameter
Positive supply current
(quiescent)
Negative supply current
(quiescent)
Dynamic range
Linearity
Pin
Min.
14, 15
Value
Typ.
28
Max.
35
Units
Conditions
mA
V
CC
= +5.0V
ALL V
EE
Pins
75
70
-1
-1
-1.25
13
13
13
13
13
13
13
17, 18,
19
13
13
27, 28
9, 10
±0.5
-0.59
1.30
18
-5
±20
-0.1
150
180
175
210
mA
mA
dB
dB
V
EE
= -5.0V See note 1
V
EE
= -5.0V See note 2
100 to 400MHz See note 1, 3
See note 1, 4
T
CASE
= -55°C
T
CASE
= +25°C
T
CASE
= +125°
C
+1
+1
+1.25
1.75
21
±30
+0.25
-05
-0.54
10
16
1.5:1
450
-0.49
+0.5
2.00
24
+5
dB
dB
dB
V
mV/dB
%
%
V
mV/°C
V
V
Video output range
Video slope
Video slope variation
Video slope adjust range
Video offset
Video offset variation
Video offset adjust range
Video trim reference
voltage
Video output impedance
Video rise time
Input VSWR
RF bandwidth
See note 5
R
G
= 1k
to 2.2k
T
CASE
= +25°C
R
O
= 1k
to 2.2k
ns
MHz
See note 8
10% - 90% (60dB step) See note 7
Zs = 50
See note 7
T
CASE
= +25°C RFIN = -70dBm
See notes 2, 7
See notes 2, 6, 7
R1 = 50
single ended, See note 2
RF limiting range
RF limited output level
RF output impedance
Phase variation with RF
Input level
Phase tracking between
units
9, 10
9, 10
9, 10
-3.0
60
-1.0
50
15
+1.0
dB
dBm
Single ended See notes 2, 8
Degrees
Freq = 300MHz RF
IN
= -60 to +10dBm
See notes 2, 7
3
Degrees
T
CASE
= +25°C FREQ = 300MHz
See notes 2, 7
Notes
1 RF output buffer OFF (pin 8 disconnected from 0V)
2 RF output buffer ON (pin 8 connected to 0V)
3 Minimum dynamic range under any single set of operating conditions
4 Log linearity guaranteed for pin = -64dBm to +6dBm for ALL supply, temperature and frequency conditions
5 Full range of supply, temperature and frequency conditions
6 Input limiting range typically -50dBm to +10dBm
7 Not tested, but guaranteed by characterisation
8 Not tested, but guaranteed by design
Data Sheet 210892 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web:
www.plesseysemi.com
3
PS13201
The PS13201 CANNOT be GUARANTEED to operate below 100MHz and meet the electrical characteristics shown
above. However, characterisation has shown that the device can still function adequately down to frequencies of 50MHz,
with the following reservations:-
1. The video bandwidth is fixed to approx 40MHz a certain amount of carrier breakthrough on the video O/P
(pin 13) will occur, with input signal frequencies below 100MHz.
2. There are 2 RF coupling capacitors (20pF) on-chip, which couple the output signal from stage 3 to the
input of stage 4 (ref Fig. 24). These can introduce undesirable limiting phase performance for input signal
frequencies below 100MHz.
PRODUCT DESCRIPTION
The PS13201 is a complete monolithic successive detection Log/limiting amplifier which can operate over an input
frequency range of 100MHz to 500MHz. Producing a log/lin characteristic for input signals between -64dBm and
+6dBm, the log amplifier can provide an accuracy of better than
±1.00dB
at case temperatures of -55°C and
+25°C and an accuracy of better than
±1.25dB
at +125°C. The dynamic range is better than 75dB over a
frequency range of 100MHz to 400MHz. The graph in fig 4 shows how the dynamic range is guaranteed over
frequency.
Data Sheet 210892 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web:
www.plesseysemi.com
4
PS13201
The PS13201 consists of 6 Gain stages, 7 Detector stages, a limiting RF Output buffer and a Video Output amplifier.
The power supply connections to each section are isolated from each other to aid stability.
The PS13201 consumes 1.1W of power when ALL parts of the circuit are powered up from a
±5.0V
power supply. As
the circuit uses a differential architecture, the power consumption of the RF gain/detector stages and RF Output Buffer
will be independent of RF input signal level. However, the Video Output (pin 13) is driven by a single ended emitter
follower and so the power consumption of the Video amplifier will vary with RF input signal level between pins 27 and
28.(upto 10mA over 2V video output range with max video load of 200 //20pF) The PS13201 has a high RF gain
(>50dB) across a wide bandwidth (>450MHz) when the limiting RF Output Buffer is enabled. The limiting RF Output Buffer
provides a balanced Limited Output level of nominally –1.0dBm on each RF Output connection (pin 9 and 10), for RF
input signal levels on pins 27 and 28 in excess of –50dBm.
The limiting RF Output Buffer can be isolated from the other sections of the PS13201, by disconnecting the RF Output
Buffer GND (pin 8) from 0V, and leave the pin floating. This feature aids stability in applications NOT requiring a Limited
RF Output signal, and lowers the power consumption of the PS13201 to 0.95Watts, when the other sections are
powered up from a
±5.0V
power supply.
Each of the Gain and Detector stages has approximately 12dB of gain, and a significant amount of on-chip RF
decoupling (200pF per stage), also to aid stability. The Video amplifier provides a positive going output signal proportional
to the log of the amplitude of an RF input applied between pins 27 and 28. The gain and the offset of the Video amplifier
can be adjusted by 3 resistors; RG , RT , and RO which are connected to Gain adjust (pin 19),Trim reference (pin
18) and Offset adjust (pin 17). With RT set to 1.5k∧ , RG can be set to any value between 1k and 2k2 and achieve a
range in Video Slope of
±20%,
centred on 21mV/dB. Similarly, RO can be set to any value between 1k and
2.2K and achieve an offset range of
±0.5V,
which should allow the Video Offset to be trimmed to 0V if required.
The RF input pins (27 and 28) have a 50 terminating resistor connected between them on–chip. These are
capacitively coupled to the I/P gain stage with 20pF on-chip capacitors. (Refer to APPLICATION NOTES section for
information on how to connect an RF input signal to the device).
Data Sheet 210892 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web:
www.plesseysemi.com
5
